Lead Physical Design Engineer

Lead block-level and full-chip ASIC Physical Design activities.

Perform Floorplanning, Power Planning, Placement, CTS, Routing, Physical Verification, and Signoff Closure.

Analyze and resolve timing, power, signal integrity, EMIR, and DRC/LVS issues.

Coordinate with RTL, DFT, Verification, Package, and Foundry teams throughout the project lifecycle.

Review technical deliverables and ensure adherence to project quality standards.

Mentor junior Physical Design engineers and lead technical capability development initiatives taken for physical design.

Participate in customer technical discussions, project reviews, and status reporting.

Drive automation initiatives and continuous improvement of Physical Design methodologies.

Support proposal preparation, effort estimation, and resource planning for new projects.

Ensure successful project execution and on-time tape-out delivery.

Lead training & development initiatives in physical design domain

Proven experience in advanced technology nodes (28nm and below preferred).

Experience in full-chip or block-level Physical Design flow including Floor planning, Placement, CTS, Routing, Timing Closure, Power Optimization, Physical Verification, and Signoff.

Experience in working with global semiconductor companies, design service organizations, or fabless IC companies will be preferred.

Experience leading small and medium engineering teams and coordinating project execution is highly desirable.

Experience in both Cadence and Synopsys design environments is preferred.

Experience in training and development activities will be considered as a plus.

Strong understanding of CMOS fundamentals, ASIC design flow, and semiconductor manufacturing process

Experience with industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, Calibre, or equivalent.

Knowledge of scripting languages such as TCL, Perl, Python, or Shell scripting.

Strong expertise in end-to-end ASIC Physical Design implementation.